Routability-Driven Packing: Metrics And Algorithms For Cluster-Based FPGAs

Most of an FPGA s area and delay are due to routing Considering routability at earlier steps of the CAD ow would both yield better quality and faster design process In this paper we discuss the metrics that a ect routability in packing logic into clusters We are presenting a routability driven clustering method for cluster based FPGAs Our method packs LUTs into logic clusters while incorporating routability metrics into a cost function Based on our routability model the routability in timing driven packing algorithm is analyzed We integrate our routability model into a timing driven packing algorithm Our method yields up to improvement in terms of the minimum number of routing tracks compared to VPack on average The average routing area improvement is over VPack and over t VPack